1. Field of the Invention
The present invention relates to a method for manufacturing a flash memory device, and more particularly to a method for manufacturing a flash memory device with dual floating gates and two bits per cell.
2. Description of the Related Art
In the last decade, semiconductor memories have been the fastest growing segment of the semiconductor industry, with the large increase due to the rapid growth of digital electronics market with multiplying applications. Moreover, flash electrically programmable read only memories devices (EPROM) are being produced in larger quantities. Lately, high-density flash memory has been expected to share a certain part of the large computer external storage device market. One of the goals in the fabrication of flash EPROM is the production of a memory circuit that is capable of storing a maximum amount of information using a minimum amount of semiconductor surface area. However, photolithographic limits imposed by conventional semiconductor processing technology impede the achievement of this goal. Thus, the inability to pattern and etch semiconductor features closed together prevents a memory cell from occupying a smaller portion of a semiconductor's surface. Another goal of flash EPROM manufacturing is use of a simple cheap high yielding process. Many previous methods to reduce device size add too much complexity and cost.
Flash EPROM frequently uses a floating gate avalanche injection metal oxide semiconductor (FAMOS) structure to store information. Floating gate dimensions in a FAMOS memory cell are conventionally established with reference to minimum photolithographic limits and therefore produce undesirable large memory cells. A conventional configuration for an EPROM device is the stacked gate structure as shown in FIG. 1. Source 12 and Drain 14 regions are formed in substrate 10. The floating gate 16 overlies the channel region, the area between the source and drain. The control gate 18 overlays the floating gate 16. An insulating structure 20 insulates the substrate, floating gate and control gate. The minimum size of the conventional stacked gate structure is determined by the photolithographic limits which determine the floating gate, control gate, source and drain widths.
In view of the drawbacks of the prior method used to manufacture flash memory devices set forth, it is very necessary to provide a method that can overcome the photolithography limits, meanwhile, reduce the cost and complexity amid the process of manufacturing the flash memory devices. It is towards those goals that the present invention is specifically directed.